Nedit print4/1/2024 It as if I need to compile / update the cell somehow. Note: I get the same problem if I remove a pin from the verilog code and symbol of the old cell. ![]() My Setup simulator/dir/Host simulator is "Spectre" ![]() Removing my verilog symbol and placing in the that symbol causes no problem. I have another verilog file form an old employee that I copied into my lib. Either add one of these views to: Library: ap_lib Cell: firstorder_sigmadelta or modify the view list to contain an existing view. After clicking Netlist and Run I get the error:ĮRROR: Netlister: unable to descend into any of the views defined in the view list: "veriloga" for instance I14 in cell SigmaDelta_sim. The schematic simulates just fine until I use the hierachy editor to switch in a verilog view. View List: spectre cmos_sch schematic veriloga ahdl I edited the veriloga.va file and matched up the veriloga and symbol pins. File->New->Create VIEW Name: symbol TOOL: Composer-Symbol File->New->Create VIEW Name: veriloga TOOL: VerilogA-EditorĢ. I am having a problem trying to simulate with a verilog-a file. Title: Verilog simulation: Can't descend into cell views ![]() Message started by aprior on Apr 6 th, 2006, 4:05pm The Designer's Guide Community Forum - Print Page The Designer's Guide Community Forumĭesign Languages > Verilog-AMS > Verilog simulation: Can't descend into cell views
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